Chemical mechanical polishing (CMP) process is a mainstream planarization process in current semiconductor fabrication technology. Specifically, CMP process uses a method combining chemical grinding material with mechanical polishing to planarize the surface of wafer. In general, the mechanism of CMP process is as follows: a large amount of polishing fluid containing quartz sand particles is disposed on a polishing pad; materials on the surface of the wafer, especially on the protruding areas of the wafer, may react with the polishing fluid, and thus form a surface layer that can be easily removed; as the surface of the wafer moves relative to the polishing pad, the surface layer may be mechanically removed under the pressure applied by the polishing particles, and as a result, the surface of the wafer may be planarized.
Because the CMP process utilizes the interplay of chemical reaction and physical removal as well as other effects, the CMP process may be affected by many factors, such as the size of the polishing particles, the property of the polishing pad, the applied pressure, the relative speed between the polishing pad and the wafer, etc. Such factors may all have significant influence on the surface profile of the chip obtained after the CMP process. In some cases, when one or more of the above factors are not in the optimal condition, the planarization process may not reach desired results.
In order to reduce the production cost of a CMP process, a reasonable prediction on the surface profile of the chip to be obtained after the CMP process may be required. Specifically, hot spots that may appear on the chip surface may be pre-evaluated. Such hot spots may be the spots where the thickness of the pattern on the chip surface exceeds a predetermined thickness range, or where the difference between the height of the pattern on the chip surface and the height of a reference plane exceeds a predetermined height range, including microscopically raised and recessed spots on the chip surface. Hot spots may lead to a number of problems such as short circuits caused by material residue of the CMP process, graphic bridging due to the height difference on the surface of the silicon wafer exceeding the process window of the photolithography process, the resistance and capacitance values exceeding specifications during electrical testing of the wafer, etc. The surface profile of a wafer to be obtained after a CMP process is usually predicted by CMP simulation software.
According to existing technology, the flow to predict the surface profile of a wafer after a CMP process usually includes inputting a chip pattern layout, grid-partitioning the chip pattern layout, calculating the pattern characteristics of the grids, using the calculated grid geometry characteristics as parameters in the CMP simulation software to simulate the CMP process, and finally, outputting the hot spots.
However, using the existing method described above to predict the surface profile of a chip obtained after a CMP process may often lead to inaccurate predictions. The disclosed CMP simulation method and the simulation device are directed to solve one or more problems set forth above and other problems in the art.